This invention relates to a proximity sensor for detecting the passing of a ferromagnetic article such as gear teeth, and more particularly to such a sensor comprising an assembly of a magnet and an integrated circuit chip having two Hall elements with their outputs connected differentially, the chip being mounted at one pole end of the magnet.
The integrated circuit chips of such prior art proximity sensors almost always include an essentially linear Hall-voltage amplifier for amplifying the differential Hall output voltage. Also included in many such dual Hall integrated circuits is a Schmitt trigger circuit for producing a binary output signal that changes from one level (a standby level) to the other binary level (an action level) when a ferrous article approaches to within a critical distance at which the difference in the magnetic field, normal to a major face of the chip, exceeds a predetermined magnitude. These circuits are normally DC connected so that the sensor is capable of sensing passing ferrous articles at zero rate (e.g. one a year) up to a high rate (e.g. 100 KHz).
In the production of such sensors capable of sensing down to the zero rate, it has always been difficult to constantly obtain a zero output signal under the condition that there is no nearby ferrous article. Or, in the case of manufacturing a sensor to produce a binary signal of frequency corresponding to the passage of ferrous teeth in an adjacent rotating gear, wherein the mean value of the binary output signal is desirably near 50%, control of this mean value is also difficult for the same reasons: namely, that every factor that affects the output signal bias or offset must be controllable, and there are many such factors some of which are described below.
The offset of the differential output Hall voltage varies from integrated circuit chip to chip due to lack of repeatability of the dimensions of the Hall elements themselves. Slight misregistrations in successive mask registrations during manufacture of integrated circuits is but one of the numerous factors to which offset control is related. An approach for reducing the offset voltage in an integrated Hall element entailing surrounding the Hall element by a stress equalizing moat is described by Higgs and Humenick in U.S. Pat. No. 4,578,692 issued Mar. 25, 1986.
The amplifier itself would ideally produce an output voltage of zero when the amplifier input is zero, but as a practical matter, the amplifier generally has an offset voltage (with zero input voltage) that is for example owing to imbalances in pairs of transistors and pairs of resistors.
In his patent U.S. Pat. No. 4,709,214 issued Nov. 24, 1987, Higgs reduces the offset voltage of the Hall voltage amplifier by employing an extraordinarily large pair of differential amplifier transistors and positioning them on the chip symmetrically about an axis of the heat generating Hall element.
The input voltage of a Schmitt trigger circuit at which its output changes from a first level to another (often referred to as the operate voltage) varies from one integrated circuit to another again due to such factors as variation from chip to chip of transistor parameters and resistor values. The production of more predictable integrated Schmitt trigger circuits is accomplished as described in the U.S. Pat. No. 4,705,964 issued to Higgs that issued Nov. 10, 1987. This method calls for an adjustment of resistor values at the end of chip manufacture to compensate all Schmitt trigger offset factors.
In dual-Hall ferrous-article proximity sensors, Higgs and Gibson first recognized and provided a partial solution to a fourth factor contributing to overall offsets: namely, the magnetic field strength is generally not uniform over the pole end of a magnet, although it shows some symmetry about the magnet axis. And, shape of the magnetic field strength varies from magnet to magnet. Such problems are disclosed by Higgs and Gibson in their patent U.S. Pat. No. 4,859,941 issued Aug. 22, 1989. Thus to arbitrarily mount the dual Hall integrated circuit chip just anywhere on the magnet pole end invariably leads to an offset contribution due to the different field strengths at the first and second of the Hall elements respectively. A more microscopic view of the field at the pole end of a magnetic field reveals a random noise-like pattern of field strength superimposed on the roughly symmetrical profile. The solution provided in the patent is to sandwich a ferrous pole piece of particular shape between the magnet and the chip to flatten and smooth the irregularities in magnet generated field seen by the chip. A typical assymmetrical magnet field as a function of position at a pole end is shown as curve S in FIG. 1 or it may be closer to symmetrical as illustrated by curve M.
The same problem is addressed in a similar way by Kawaji and Gilbert in their patent application U.S. Pat. No. 4,935,698 issued June 19, 1990.
Integrated circuit chips containing the dual Hall elements are usually protected by encapsulation in a plastic package before being mounted on a magnet for ferromagnetic article sensing. Various degrees of tipping of the chip in the package or the package on the magnet can occur leading to offset in the output signal.
The five above-noted patents are assigned to the same assignee as is the present invention.
Reduction of the elemental sources of overall integrated circuit offset voltage, by one or all of the patented approaches noted above may be advantageous in combination with the features of the present invention. However, reduction of those elemental sources alone cannot as a practical matter be accomplished in such a way as to compensate for all the sources of offset.
It is an object of the present invention to provide a method for making a dual-Hall ferrous-article proximity sensor wherein the offset from each of the above-noted sources are self-compensating.
It is another object of the present invention to provide a dual Hall ferrous-article proximity detector that has an output voltage with one parameter meeting a predetermined criteria that accounts for all sources of offset voltage therein.